1. Field of the Invention
The invention relates generally to the semiconductor power devices. More particularly, this invention relates to an improved and novel device configuration and manufacturing process to provide electronic device and resistor with high sheet resistance and capacitor with high capacitance by employing a single polysilicon process.
2. Description of the Prior Art
Conventional processes for manufacturing device component that has resistor with high sheet resistance and capacitor with high capacitance generally apply a double polysilicon process. The processing steps for making double polysilicon components involve multiple masks and additional processing steps. These types of device components become more costly to implement. The process of manufacture becomes more time consuming and complicated. Furthermore, the device reliability is also adversely affected due to the more complicate manufacturing processes. As the device components that comprises resistor of high sheet resistance and capacitor with high capacitance are broadly implemented in analog circuit and power integrated circuit (IC) applications, there are great demand to resolve these technical limitations and difficulties.
In U.S. Pat. No. 5,489,547, entitled “Method of fabricating semiconductor device having polysilicon resistor with low temperature coefficient” Erdeljac et al. disclose a semiconductor device as shown in FIG. 1A. The semiconductor device includes a P type polysilicon resistor (56) with a moderate sheet resistance. A double-level polysilicon process is applied to form a resistor of low temperature coefficient. The process also produces n and p-channel transistors (44, 50), a capacitor having upper and lower n type polysilicon capacitor plates (36, 26), an n type polysilicon resistor (32) having a high sheet resistance, and an n type resistor (34) having a low sheet resistance. The p type doping used to form the source/drain regions (48) of p-channel transistor (50) counter dopes n type second level polysilicon to form p type polysilicon resistor (56) without effecting capacitor plates (36, 26) or the n type resistors (32, 34). As discussed above, the device as disclosed in this patented invention applies the double polysilicon processes that generally involve multiple masks and additional processing steps. These types of device components become more costly to implement. The process of manufacture becomes more time consuming and complicated.
Tsui et al. disclose in another U.S. Pat. No. 6,054,359 a high sheet resistance polysilicon resistance for integrated circuits. The high sheet resistance polysilicon resistor is manufactured with a two-layer polysilicon process. Referring to FIG. 1B, Tsui et al. disclose process for forming FET gate electrodes and capacitor bottom electrodes from a polycide layer. Then the processes proceed with depositing a thin inter-polysilicon oxide (IPO) layer to form the capacitor inter-electrode dielectric. A doped polysilicon layer and an undoped polysilicon layer are deposited and patterned to form the resistor. Since the undoped polysilicon layer has a very high resistance, the doped polysilicon layer predominantly determines the resistance. The doped polysilicon layer can be reduced in thickness to further increase the sheet resistance for mixed-mode circuits. Again, a double polysilicon process is applied that still has the above-discussed technical limitations and difficulties.
Therefore, a need still exists in the art of semiconductor device design and manufacture to provide new manufacturing method and device configuration in forming the semiconductor devices with high sheet resistance and high capacitance with simplified manufacturing processes such that the above discussed problems and limitations can be resolved.